Differential digital line receivers and operational amplifiers, each using a differential amplifier as an input stage, convert differential input signals, represented by the difference between two input signals, to a non-differential (single-ended) output signal. A conventional differential input stage 10 is diagrammed in FIG. 1 and is similar to that disclosed in "Analysis and Design of Analog Integrated Circuits", by Gray and Meyer, 1984, FIG. 12.31(a),page 742. Stage 10 converts the differential input signal to a single-ended output signal for driving conventional buffer 11. Input transistors 12 and 13, a differential pair, respond to the differential input signal applied to the inputs IN and IN'. Transistors 12 and 13 in turn couple to load transistors 14 and 15 at corresponding nodes N1' and N1, node N1 being the output of stage 10. The source electrodes of load transistors 14 and 15 couple to Vcc, the most positive supply node. The load transistors 14 and 15 are further coupled gate-to-gate and to the drain electrode of transistor 14 at node N1' to form a conventional current mirror. The source electrodes of input transistors 12 and 13 and the input to current source 16 are coupled together at node N2. The output of source 16 couples to Vss, the most negative supply node (usually at ground potential or 0 volts.) An exemplary idle operating condition has Vss at 0 volts and the inputs IN and IN' biased to a bias voltage that is substantially equal one-half of Vcc, or Vcc/2. This condition results in nodes N1 and N1' having substantially the same voltage (Vcc/2) with respect to Vss.
A common mode signal, a signal having substantially equal amplitude and polarity on both inputs IN and IN' with respect to Vss, impressed on the bias voltage on inputs IN and IN' causes node N2 to follow the common mode signal. The voltages on nodes N1 and N1' will not change appreciably in response if the current source 16 is "perfect", i.e., it has an effectively infinite impedance. Such is usually not the case and with the finite impedance of the source 16, the voltage on node N2 does not precisely follow the common mode signal causing current passing through transistors 12 and 13 to vary. This causes some variation in voltage on nodes N1 and N1'. This condition is aggravated with short-channel MOS transistors, transistors having a channel length approaching the thickness of the junction depletion layer of the transistor, adapted to operate as the current source 16 since short-channel MOS transistors have a lower output impedance than long-channel transistors. The current mirror of transistors 14 and 15 reduce the voltage variation on node N1 in response to the common mode signal by counteracting the variation in current passing through transistor 13 with a substantially equal current variation passing through transistor 15 in response to the current passing through transistors 12 and 14. This further reduces the voltage variation on node N1 but not on node N1'. However, operation of the current mirror is not perfect and the voltage variation on node N1 in response to the common mode signal is not completely eliminated.
A small-signal differential input signal impressed on the bias voltage on inputs IN and IN' cause the voltages on nodes N1 and N1' to vary inversely. However, capacitive loading on node N1', caused by the combined capacitance of the gates of transistors 14 and 15, limits the frequency response of the current mirror of transistors 14 and 15, limiting the overall frequency response and speed of stage 10. This capacitive loading of node N1' also increases the common mode signal response of the stage 10 with increasing frequency of the common mode signal since at higher frequencies the current mirror of transistors 14 and 15 cannot fully compensate for the current variations through transistor 13.
Due to the high overall gain (approximately 100) of the stage 10, a large-signal differential input signal exceeding a relatively small predetermined amplitude will cut-off transistors 13 or 15, introducing considerable distortion in the output signal and limiting the dynamic range of the stage 10. This is an overload condition which adds delay to the response time of the stage 10, when the overload condition is removed or reversed in polarity, due to the recovery time necessary for the affected transistors to reestablish the proper operating conditions.